library verilog;
use verilog.vl_types.all;
entity PWM_COMPARATOR is
    port(
        i_compare_value : in     vl_logic_vector(6 downto 0);
        i_compare_set_value: in     vl_logic_vector(6 downto 0);
        o_compare_result: out    vl_logic
    );
end PWM_COMPARATOR;
